november 2009 doc id 16831 rev 1 1/9 9 dpiulc6 esd protection for internal displayport? features compliant with displayport 1.1a iec 61000-4-2 level 4 compliant ultralarge bandwidth (> 5 ghz) low capacitance variation: 0.05 pf 100 10% differential impedance (100% compatible with 100 differential layout) 500 m pitch for easy layout complies with the following standards iec 61000-4-2 level 4 ? 15 kv (air discharge) ? 8 kv (contact discharge) mil std 883g-method 3015-7: class 3b ? 8 kv hbm (human body model) vesa displayport st andard version 1.1a description the DPIULC6-6DJL device provides fully integrated esd protection ensuring full system robustness as required by the displayport specification. differentiated protection dedicated to each link ensures fu ll compliance with the displayport specification. the bandwidth of each circuit ensures full transparency to the displayport signals. the DPIULC6-6DJL is packaged in dfn 5x6. figure 1. schematic diagram (top view) tm: displayport is a tradem ark of the video electronics standards association (vesa) dfn 5x6 18 leads nc d1+ d1 - gnd d2+ d2 - gnd aux+ aux - nc d1+ d1 - gnd d2+ d2 - gnd aux+ aux - nc d1+ d1 - gnd d2+ d2 - gnd aux+ aux - nc d1+ d1 - gnd d2+ d2 - gnd aux+ aux - nc pins must be connected to ground www.st.com
characteristics dpiulc6 2/9 doc id 16831 rev 1 1 characteristics table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit t stg storage temperature range -55 to +150 c t j operating junction temperature range -40 to +125 c t l maximum lead temperature for soldering during 10 s 260 c table 2. electrical characteristics: high speed differential pairs (t amb = 25 c) symbol parameter test conditions value unit min. typ. max. i rm leakage current v = 3.0 v - - 100 na v br breakdown voltage t a = 25 c, i r = 1 ma 6 - - v v cl clamping voltage (any i/o pin to ground) t p = 8/20 s i pp = 1 a - - 12 v i pp = 5 a - - 17 c i/o -gnd capacitance between i/o and ground v r = 0 v, f=1 mhz - - 1.5 pf v r = 0 v, f = 1.4 ghz - - 1.5 c i/o -gnd capacitance variation between 2 lines of the same pair v r = 0 v, f = 1.4 ghz - 0.05 0.12 pf z diff differential impedance between input and output t r (20%-80%)=130 ps 90 100 110 table 3. electrical characteristics: auxiliary link (t amb = 25 c) symbol parameters test conditions value unit min. typ. max. i rm leakage current v = 3.0 v - - 100 na v br breakdown voltage between v bus and ground t a = 25 c, i r = 1 ma 6 - - v v cl clamping voltage t p = 8/20 s i pp = 1 a - - 12 v i pp = 5 a - - 17 c i/o-gnd capacitance between i/o and ground v r =0 v, f=1 mhz - 42 50 pf f c cut-off frequency -7.0-mhz
dpiulc6 characteristics doc id 16831 rev 1 3/9 figure 2. frequency response (typical value) 300k 1m 3m 10m 30m 100m 300m 1g 3g -12 -9 -6 -3 0 db f (hz) passband attenuation -3 db point attenuation (0.8 - 4 ghz) average performance (50 system) 0.05 db 4.7 ghz < 0.4 db 0.1 db @ 900 mhz 0.4 db @ 1.8 ghz figure 3. leakage current versus junction temperature (typical values) figure 4. differential t dr measurement at 130 ps (20 - 80%) 0.1 1.0 10.0 100.0 1000.0 25 50 75 100 125 i r (na) v r =v rm 3v t j (c) maximum 103.75 minimum 97.46 figure 5. eye diagram at 2.7 gbps (pcb alone) figure 6. eye diagram at 2.7 gbps (pcb + DPIULC6-6DJL)
application information dpiulc6 4/9 doc id 16831 rev 1 2 application information figure 9. displayport internal schematic on source side figure 7. esd response to iec 61000-4-2 (+8 kv contact discharge) figure 8. esd response to iec 61000-4-2 (+8 kv contact discharge) v cl 50 v/div 20 ns/div 50 v/div v cl 20 ns/div 30 29 28 27 26 25 24 23 22 21 20 19 aux_pwd dpi internal connector reserved h_gnd aux_ch- aux_ch+ h_gnd ml_lane0+ ml_lane0- h_gnd ml_lane1+ ml_lane1- h_gnd vtx_bias 3.3v DPIULC6-6DJL aux_pwd aux_ch- aux_ch+ ml_lane0+ ml_lane0- ml_lane1+ ml_lane1- 1 esdalc6v1-1m2
dpiulc6 application information doc id 16831 rev 1 5/9 figure 10. displayport internal schematic on sink side 30 29 28 27 26 25 24 23 22 21 20 19 aux_pwd dpi internal connector reserved h_gnd aux_ch- aux_ch+ h_gnd ml_lane0+ ml_lane0- h_gnd ml_lane1+ ml_lane1- h_gnd vrx_bias 3.3v aux_pwd aux_ch- aux_ch+ ml_lane0+ ml_lane0- ml_lane1+ ml_lane1- DPIULC6-6DJL esdalc6v1-1m2 1
ordering information scheme dpiulc6 6/9 doc id 16831 rev 1 3 ordering information scheme figure 11. ordering information scheme dpi ulc 6 - 6 xxx ultralow capacitance breakdown voltage vbr = 6 v number of lines package djl = dfn 5x6 - 6 xxx dipsplayport internal djl = dfn 5x6
dpiulc6 package information doc id 16831 rev 1 7/9 4 package information epoxy meets ul94, v0 lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. dfn 5x6 package dimension definitions table 4. dfn 5x6 package dimension values ref. millimetres inches min. typ. max. min. typ. max. a 0.80 0.90 1.0 0.031 0.035 0.039 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.18 0.25 0.30 0.007 0.010 0.012 d 5.90 6.00 6.10 0.232 0.236 0.240 d2 4.00 4.15 4.25 0.157 0.163 0.167 e-0.5- -0.020- e 4.90 5.00 5.10 0.193 0.197 0.201 e2 3.00 3.15 3.25 0.118 0.124 0.128 l 0.45 0.55 0.65 0.020 0.022 0.025 b e l e d a a1 e2 d2 19 10 18 seating plane
ordering information dpiulc6 8/9 doc id 16831 rev 1 5 ordering information 6 revision history figure 13. footprint recommendations in millimetres (inches) figure 14. marking 3.15 (0.124) 0.75 (0.030) 0.5 (0.020) 0.33 (0.013) 0.25 (0.010) 4.25 (0.167) 4.15 (0.163) 3.8 (0.149) 5.3 (0.209) y ww zz xxx xxx: marking zz: manufacturing location y: year ww: week table 5. ordering information order code marking package weight base qty delivery mode DPIULC6-6DJL dpil66 dfn 5x6 18 leads 78.8 mg 3000 tape and reel table 6. document revision history date revision changes 27-nov-2009 1 initial release.
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